EzDev.org

make interview questions

Top 15 make interview questions

18947 Jobs openings for make


Using make on OSX

I have a macbook I'm trying to do some development on. I have a program I want to build, and when I went to use make to build it I got a "command not found" error. I did some google and SO searches and it doesn't look like this is a common problem. Why don't I have make installed and how do I get it? I'm extra confused because I know I used it relatively recently (in the past month or so) when I was on this laptop.


Source: (StackOverflow)

Can you make valid Makefiles without tab characters?

target: dependencies
    command1
    command2

On my system (Mac OS X), make seems to require that that Makefiles have a tab character preceding the the content of each command line, or it throws a syntax error.

This is an annoyance when creating or editing Makefiles because I have my editor set up to be all-spaces-all-the-time.

Can you make valid Makefiles without tab characters?


Source: (StackOverflow)

How "make" app knows default target to build if no target is specified?

Most linux apps are compiled with

make
make install clean

As i understood, make takes names of build targets as arguments. so "install" is a target that copies some files and after that "clean" is a target that removes temporary files.

But what target "make" will build if no arguments are specified (first command in my example)?


Source: (StackOverflow)

How to have GNU make explicitly test for failure?

After years of not using make, I find myself needing it again, the gnu version now. I'm pretty sure I should be able to do what I want, but haven't figured out how, or found an answer with Google, etc.

I'm trying to create a test target which will execute my program a number of times, saving the results in a log file. Some tests should cause my program to abort. Unfortunately, my makefile aborts on the first test which leads to an error. I have something like:

# Makefile
# 
test:
        myProg -h > test.log              # Display help
        myProg good_input >> test.log     # should run fine
        myProg bad_input1 >> test.log      # Error 1
        myProg bad_input2 >> test.log      # Error 2

With the above, make quits after the bad_input1 run, never getting to the bad_input2 run.


Source: (StackOverflow)

What is the difference between gmake and make?

I am trying to understand the difference between 'gmake' and 'make'?

On my linux box they are identical:

% gmake --version
GNU Make 3.81
Copyright (C) 2006  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

% make --version
GNU Make 3.81
Copyright (C) 2006  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

I am guessing this isn't the same on all platforms? Is there a good reason to use one over the other?
Is there some historical significance to why there are the two names?


Source: (StackOverflow)

What is your experience with non-recursive make? [closed]

A few years ago, I read the Recursive Make Considered Harmful paper and implemented the idea in my own build process. Recently, I read another article with ideas about how to implement non-recursive make. So I have a few data points that non-recursive make works for at least a few projects.

But I'm curious about the experiences of others. Have you tried non-recursive make? Did it make things better or worse? Was it worth the time?


Source: (StackOverflow)

Why always ./configure; make; make install; as 3 seperate steps?

Everytime you compile something from source, you go through the same 3 steps:

$ ./configure
$ make
$ make install

I understand, that it makes sense to divide the installing process into different steps, but I don't get it, why each and every coder on this planet has to write the same three commands again and again just to get one single job done. From my point of view it would make totally sense to have a ./install.sh script automatically delivered with the source code which contains the following text:

#!/bin/sh
./configure
make
make install

why would people do the 3 steps seperately?


Source: (StackOverflow)

Why does make think the target is up to date?

This is my Makefile:

REBAR=./rebar
REBAR_COMPILE=$(REBAR) get-deps compile

all: compile

compile:
    $(REBAR_COMPILE)

test:
    $(REBAR_COMPILE) skip_deps=true eunit

clean:
    -rm -rf deps ebin priv doc/*

docs:
    $(REBAR_COMPILE) doc

ifeq ($(wildcard dialyzer/sqlite3.plt),)
static:
    $(REBAR_COMPILE) build_plt analyze
else
static:
    $(REBAR_COMPILE) analyze
endif

I can run make compile multiple times and get

aromanov@alexey-desktop:~/workspace/gm-controller/lib/erlang-sqlite$ make compile
./rebar get-deps compile
==> erlang-sqlite (get-deps)
==> erlang-sqlite (compile)

However, for some reason running make test always gives

aromanov@alexey-desktop:~/workspace/gm-controller/lib/erlang-sqlite$ make test
make: `test' is up to date.

even if the files are not compiled. The question is, why?

Running the same command directly works:

aromanov@alexey-desktop:~/workspace/gm-controller/lib/erlang-sqlite$ ./rebar get-deps compile skip_deps=true eunit
==> erlang-sqlite (get-deps)
==> erlang-sqlite (compile)
Compiled src/sqlite3_lib.erl
Compiled src/sqlite3.erl
==> erlang-sqlite (eunit)
...

Source: (StackOverflow)

Define make variable at rule execution time

In my GNUmakefile, I would like to have a rule that uses a temporary directory. For example:

out.tar: TMP := $(shell mktemp -d)
        echo hi $(TMP)/hi.txt
        tar -C $(TMP) cf $@ .
        rm -rf $(TMP)

As written, the above rule creates the temporary directory at the time that the rule is parsed. This means that, even I don't make out.tar all the time, many temporary directories get created. I would like to avoid my /tmp being littered with unused temporary directories.

Is there a way to cause the variable to only be defined when the rule is fired, as opposed to whenever it is defined?

My main thought is to dump the mktemp and tar into a shell script but that seems somewhat unsightly.


Source: (StackOverflow)

Compiling C++ on remote Linux machine - "clock skew detected" warning

I'm connected to my university's small Linux cluster via PuTTY and WinSCP, transferring files using the latter and compiling and running them with the former. My work so far has been performed in the university's labs, but today I have been doing some work at home that generated an interesting warning.

I uploaded an entire folder of stuff and, upon running the make command, I get this as the last line of output:

make: warning: Clock skew detected. Your build may be incomplete.

The resulting binary works correctly, and there doesn't seem to be any other unexpected errors in the build process.

I seem to be able to trigger the error by building after uploading some new / replacement files (I edit everything locally then upload the new version), so I'm wondering if it's something just as simple as mismatched file modification times? Or something more concerning?

So, should I be worried? How do I fix/prevent this?


Source: (StackOverflow)

What is makeinfo, and how do I get it?

I'm trying to build GNU grep, and when I run make, I get:

[snip]
/bin/bash: line 9: makeinfo: command not found

What is makeinfo, and how do I get it?

(This is Ubuntu, if it makes a difference)


Source: (StackOverflow)

How do I force make/gcc to show me the commands?

I'm trying to debug a compilation problem but I cannot seem to get GCC (or maybe it is make??) to show me the actual compiler and linker commands it is executing. Here is the output I am seeing:

  CCLD   libvirt_parthelper
libvirt_parthelper-parthelper.o: In function `main':
/root/qemu-build/libvirt-0.9.0/src/storage/parthelper.c:102: undefined reference to `ped_device_get'
/root/qemu-build/libvirt-0.9.0/src/storage/parthelper.c:116: undefined reference to `ped_disk_new'
/root/qemu-build/libvirt-0.9.0/src/storage/parthelper.c:122: undefined reference to `ped_disk_next_partition'
/root/qemu-build/libvirt-0.9.0/src/storage/parthelper.c:172: undefined reference to `ped_disk_next_partition'
/root/qemu-build/libvirt-0.9.0/src/storage/parthelper.c:172: undefined reference to `ped_disk_next_partition'
collect2: ld returned 1 exit status
make[3]: *** [libvirt_parthelper] Error 1

What I want to see should be similar to this:

$ make
gcc -Wall   -c -o main.o main.c
gcc -Wall   -c -o hello_fn.o hello_fn.c
gcc   main.o hello_fn.o   -o main

Notice how this example has the complete gcc command displayed. The above example merely shows things like "CCLD libvirt_parthelper". I'm not sure how to control this behavior. Help? :)


Source: (StackOverflow)

List goals/targets in GNU make that contain variables in their definition

I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)). Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these variables?

I'd like to be able to get the targets for an aribitrary makefile. I'm trying to write a completion function for my shell.


Source: (StackOverflow)

How can I configure my makefile for debug and release builds?

I have the following makefile for my project, and I'd like to configure it for release and debug builds. In my code, I have lots of #ifdef DEBUG macros in place, so it's simply a matter of setting this macro and adding the '-g3 -gdwarf2' flags to the compilers. How can I do this?

EDIT: Just to clarify, when I say release/debug builds, I want to be able to just type 'make' and get a release build or 'make debug' and get a debug build, without manually commenting out things in the makefile.

$(CC) = g++ -g3 -gdwarf2
$(cc) = gcc -g3 -gdwarf2

all: executable

executable: CommandParser.tab.o CommandParser.yy.o Command.o
    g++ -g -o output CommandParser.yy.o CommandParser.tab.o Command.o -lfl

CommandParser.yy.o: CommandParser.l 
    flex -o CommandParser.yy.c CommandParser.l
    gcc -g -c CommandParser.yy.c

CommandParser.tab.o: CommandParser.y
    bison -d CommandParser.y
    g++ -g -c CommandParser.tab.c

Command.o: Command.cpp
    g++ -g -c Command.cpp

clean:
    rm -f CommandParser.tab.* CommandParser.yy.* output *.o

Source: (StackOverflow)

Compiling with g++ using multiple cores

Quick question: what is the compiler flag to allow g++ to spawn multiple instances of itself in order to compile large projects quicker (for example 4 source files at a time for a multi-core CPU)?

Many thanks.


Source: (StackOverflow)